1. Technical Field
The present invention relates in general to data processing systems and, in particular, to an improved interconnect fabric for data processing systems.
2. Description of the Related Art
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Currently, SMP computer systems employ a variety of system architectures, which exhibit varying degrees of scalability. One limitation to scalability of conventional SMP architectures is the number of queues employed to track operations (e.g., data read requests, data write requests, I/O requests, etc.) flowing throughout the system. Generally speaking, as system scale increases, the number and depth of queues required to track operations increases at greater than a linear rate. Consequently, what is needed is an improved data processing system, communication fabric for a data processing and method of data processing that reduces the number of queues utilized to track operations.